Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field‐Effect Transistor

A detailed investigation, with the help of extensive device simulations, of the effects of a spacer dielectric on the device performance of a tunnel field‐effect transistor (TFET) is reported in this chapter. The effects of varying the dielectric constant and width of the spacer are studied. It is observed that the use of a low‐
k
dielectric as a spacer causes an improvement in its ON‐state current. The device performance is degraded with an increase in the spacer width until a certain value (~30 nm), after which the dependence becomes very weak. The effects of varying the source doping concentration as well as the gate overlap/underlap are also investigated. Higher source doping or a gate‐source overlap reduces the spacer dependence of the device characteristics. A gate underlap structure, however, shows an improved performance for a high‐
k
spacer. For a given spacer, although a gate overlap or a relatively large gate underlap degrades the device performance, a small gate underlap shows an improvement in it.