Practical Source/Drain Diffusion and Body Doping Layouts for High‐Performance and Low‐Energy Triple‐Gate SOI MOSFETs

This chapter describes the impact of taking a holistic approach to designing the source and drain (S/D) structures of triple‐gate silicon‐on‐insulator metal oxide semiconductor field‐effect transistors (TG SOI MOSFETs) on their resulting performance; here the FinFET structure is considered to be realistic. The fundamental tradeoff between drive current (
I_ON
) and short‐channel effects, which should result in a negative impact on device performance, is demonstrated for devices with various S/D structures. Practical design guidelines are proposed to raise drivability and suppress the degradation in subthreshold swing in future nano‐scale TG SOI MOSFETs. It is shown that a low‐doping p‐region for nMOS device (or n‐region for pMOS device) should be put beneath the n
⁺
‐S/D for nMOS device (p
⁺
‐S/D for pMOS device) diffusion layer in order to ensure drivability while suppressing the buried‐insulator‐induced barrier‐lowering (BIIBL) effect. It is also shown that a low‐fin device with a shallow junction should be used in order to ensure drivability per unit channel width, and that a high‐fin device with a shallow junction should be used in order to achieve low standby power consumption.