A Different Way of Constructing a Clock Signal: Time-Average-Frequency

This chapter discusses the creation of a sense-of-time in the electronic world. The common approach used today for establishing a time scale on-chip is by using a phase lock loop (PLL), which is a beautiful blend of analog and digital circuit technologies. In modern chip design the mainstream design method of establishing temporal order among events is through stage-by-stage operation: the synchronous design method. The spirit of time-average-frequency (TAF) is to use two (or more) types of pulses to construct the clock pulse train and then to fulfill the need of complex application scenarios. The purpose of introducing the TAF- direct period synthesis (TAF-DPS) circuit is to address the two long-lasting problems in this field: arbitrary frequency generation (small frequency granularity) and instantaneous frequency switching. The three most often used jitter qualifiers are P2P period jitter, cycle-to-cycle (C2C) period jitter, and time interval error (TIE).