Methodology on Extracting Compact Layout Rules for Latchup Prevention

introduces the experimental methodologies to extract area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, for internal circuits, and for between I/O and internal circuits. Through detailed investigations of latchup immunity dependencies on variations of geometrical layout parameters and temperatures, compact and safe layout rules can be established for latchup prevention in a given CMOS process. Such skills are useful for foundries to provide their customers a safe process design rule without suffering latchup issues, and also helpful for IC designers to understand the latchup immunity dependencies on IC layout plans.