ComponentLevel Measurement for TLU under SystemLevel ESD Considerations

introduces a component-level TLU measurement setup with bipolar (underdamped sinusoidal) voltage trigger source. This measurement setup can evaluate the TLU immunity of single IC by monitoring the voltage/current waveforms through oscilloscope. Additionally, by applying the bipolar trigger voltage on the power pins of DUT, it can accurately simulate how a CMOS IC will be disturbed by the ESD-generated noises under the system-level ESD test. With the component-level TLU measurement setup, different types of board-level noise filter networks can be evaluated to find their effectiveness for improving the TLU immunity of CMOS ICs.