On the Use of Modulo Arithmetic Comb Filters in Sigma Delta Modulators

A novel architecture of one stage Comb decimation filters for Sigma Delta Modulators is described. It performs the decimation of a 1 bit oversampled modulator output to an arbitrary lower output frequency.

The use of modulo arithmetic throughout the filter together with the proposed algorithmic decomposition allows a low power and area efficient implementation. This also avoids the storing of the coefficients in a ROM or the generation of the coefficients with rather complicated up/down counters.

The architecture is applicablR to all comb decimation filters with sinc^R (f) response. A filter with k=3 and a programmable decimation factor has been integrated in a 3 ¿m CMOS process.