An Oversampled SigmaDelta A/D Converter Circuit Using TwoStage Fourth Order Modulator

A sigma-delta A/D converter realization using two-stage 4th order modulator architecture and 5th order digital runningsum decimation filter is presented. The analog part of the converter consist of two cascaded second order modulators. Scaling is used between the sections in order to achieve modest requirements for component matching and integrator's gain and phase. A digital running-sum filter is used for the decimation to 4fS or 2fs. A dedicated 7 instruction filter processor is designed to perform the final decimation and I/O-communication. The whole system operates on a single 5 V operation voltage.