Hardware‐Based Encryption via Generalized Synchronization of Complex Networks

We present an encryption and authentication scheme suitable for ASIC or FPGA hardware implementation, which is based on the generalized synchronization of systems showing chaotic dynamical behavior. The scheme consists of a single‐driver system, which provides two identical driven systems with a complex waveform. The driven and driving systems synchronize with correlation no higher than 1.2%. A bit‐stream derived from their outputs is then used as an encryption or authentication key. The security of the scheme is based on the fact that it is easy to generate the response of the complex systems, given an input, but hard to do a system identification. Furthermore, the spectrum of the signals of the driver and driven system reveals no information. We show that regardless of their initial state, the distant receivers synchronize within a short time, relative to their internal timescale. We validate the bit‐streams generated by the driver using the NIST test suite for randomness and have found no deviations. Finally, we provide pointers as to the practical implementation and application of the presented scheme.