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Applied Assertion-Based Verification examines the application of assertion-based verification in today's electronic design industry to address specific challenges of poor observability and controllability during the verification process. Statistics illustrating successful application of both low-level and high-level assertions are presented. While the process of writing assertions is fairly well understood by those skilled in the art-the process of creating higher-level assertion-based IP that must communicate with other components in a contemporary transaction-level modeling (TLM) simulation environment, is not. Hence, Applied Assertion-Based Verification provides a set of steps (in a tutorial fashion) for creating assertion-based IP. Applied Assertion-Based Verification provides a survey of today's ABV landscape, ranging from industry case studies to today's assertion language standardization efforts, to emerging challenges and research opportunities. In addition, it directly add esses industry process issues of developing assertion-based IP by introducing a systematic set of planning and development steps. A detailed bus protocol example is provided, which draws together the various concepts introduced throughout the text while demonstrating an effective process for developing assertion and assertion-based verification IP.