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Chip-level soft-error rate (SER) estimation can come from two sources: direct experimental measurement and simulation. Because SER mitigation decisions need to be made very early in the product design cycle, long before product Si is available, a simulation-based methodology of chip-level radiation-induced soft error rates that is fast and reasonably accurate is crucial to the reliability and success of the final product. The following contribution summarizes selected publications that are deemed relevant by the author to enable a truly chip-level radiation-induced soft error rate estimation methodology. Although the strategies and concepts described have microprocessors manufactured in bulk CMOS technologies in mind, there is no fundamental reason why they cannot be applied to other technologies and different types of integrated circuits (ICs).