Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

A Time-Domain High-Order MASH \Delta \Sigma ADC Using Voltage-Controlled Gated-Ring Oscillator

Sign In

Full text access may be available.

To access full text, please use your member or institutional sign in.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Yu, W. ; Department of Electrical Engineering, KAIST, Daejeon, Republic of Korea ; Kim, J. ; Kim, K. ; Cho, S.

In this paper, a time-domain high-order \Delta \Sigma analog-to-digital converter (ADC) using voltage-controlled gated-ring oscillator (VC-GRO) and time-domain multi-stage-noise-shaping (MASH) is introduced. To implement the high-order noise transfer function (NTF), a voltage-controlled oscillator (VCO) and VC-GRO quantizers are cascaded. Unlike conventional high-order \Delta \Sigma ADC using feedback loop, the proposed ADC has advantages that the architecture is open-loop and the quantizer resolution depends on the time resolution, thus making it attractive for deep submicron CMOS process. The performance of the proposed ADC is theoretically analyzed and simulated, including non-ideal conditions such as nonlinearity, mismatch, propagation delay of logic gates, phase noise, and sampling clock jitter.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:60 ,  Issue: 4 )