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Chip-level TSV integration for rapid prototyping of 3D system LSIs

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9 Author(s)
Hozawa, K. ; Assoc. of Super-Adv. Electron. Technol. (ASET), Tokyo, Japan ; Furuta, F. ; Hanaoka, Y. ; Aoki, M.
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For rapid prototyping of system LSIs based on three-dimension (3D) integration using through-silicon-vias (TSVs), a TSV fabrication technology for a diced chip with copper/low-k interconnections (called “chip-level TSV integration”) was developed. The two key processes of this technology are uniform substrate thinning in chip form and via-last TSV formation for nanometer-sized copper/low-k interconnection. Chip-level TSV integration will provide rapid prototyping of 3D system LSIs based on various chips with TSVs.

Published in:

3D Systems Integration Conference (3DIC), 2011 IEEE International

Date of Conference:

Jan. 31 2012-Feb. 2 2012

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