A Reconfigurable On-Chip Interconnection Network for Large Multicore Systems

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2 Author(s)

This chapter introduces the baseline reconfigurable networks-on-chip (NoC) architecture. It addresses two problems of core to network mapping and topology exploration in which the cores of a given set of input applications are physically mapped to the network and then a suitable topology is found for each individual application. Experimental results, using some multicore system-on-chips (SoC) workloads, show that this architecture effectively improves the performance of NoCs by 29% and reduces the power consumption by 9% over one of the most efficient and popular mapping algorithms proposed for conventional NoCs. The chapter extends the baseline reconfigurable NoC to a generalized reconfigurable NoC architecture. This new cluster-based structure consists of several mesh clusters alongside a reconfigurable connection fabric that handles the intercluster communication. It can support both local and global traffic patterns in an efficient manner.