Power BiCMOS process with high voltage device implementation for 20 V mixed signal circuit applications

Optimization of circuit performance and cost generally involves a trade-off between a) circuit design and die area efficiency plus shortest time to market with b) maintaining production efficiency of multiple process variants with multiple component lists. Key technology drivers were identified and redesigned in the LBC6 generation power BiCMOS process described herein to achieve a 40% die area reduction for the huge 20 V and below power IC application market. In this paper, we discuss components and their design, generic process flow, and reasoning.