A fast and area-efficiency BWC array D/A and A/D conversion scheme

A modification to D/A and A/D converters of the charge redistribution type is suggested. It reduces the silicon area requirement by a factor of two or more (up to 6.5 for 8-bit converters) and increases the speed by a similar factor, while retaining compatibility to presently used MOS fabrication processes. The scheme is sufficiently insensitive to undercuts and parasitics. Under the scheme, some of the LSB (least-significant bit) side branch capacitors are realized as a series combination of unit capacitors and the higher-bit capacitances are adjusted to make them binary-weighted to the LSB capacitances. Simulation results and an implemented binary-weighted capacitor (BWC) scheme are shown.<
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