VHDL-based system-level design methodology for multimedia signal processing applications

We propose an efficient system-level design methodology for multimedia signal processing applications, and demonstrate its applicability on a case study of MPEG-2 video decoder. The methodology offers to start from an executable specification, and supports refinement toward the register transfer level. Its primary objective is to provide the system designer with a method to design, simulate and evaluate a system through a series of abstraction levels using a VHDL based top-down modeling methodology. Sequential transformations are performed, and the initial model is partitioned in order to make the domain-specific refinements possible. The sequential model is transformed into concurrent processes. Different partitions can be quickly evaluated by moving functionality between processes. Inter-process communications via abstract communication channels are introduced. Finally the timing is refined by introducing propagation delay, and the earlier casual communication is replaced by clock-based communication.