Ultra CSP/sup TM/ Bump on Polymer structure

The wafer level Ultra CSP has the potential for DRAM and Direct Rambus/sup TM/ DRAM (D-RDRAM/sup TM/) applications for three reasons: excellent electrical performance, sufficient design margin, and low cost. To meet the desired capacitance requirements, a design concept called Bump-on-Polymer (BOP) structure was developed at Flip Chip Technologies. Three test vehicles were defined for this study. The first test vehicle is a 0.80 mm pitch 90 I/O daisy chain device to emulate a DRAM device. The second test vehicle has the same foot-print as a D-RDRAM (128/144) with 0.8 mm pitch in the x-direction and 1.0 mm pitch in the y-direction. The third test vehicle is a generic 0.50 mm pitch daisy chain device which can be bumped in 6/spl times/6, 8/spl times/8, and 10/spl times/10 array for DNP study. This paper reviews the board level thermal cycle test results on the BOP structure of these test vehicles in terms of package configuration, substrate design, solder ball size, and DNP effect. Issues in wafer level processes and reliability test conditions were also addressed. Recommendations are provided for the implementation of Ultra CSP for DRAM applications.