Wafer level package using double balls

The highest potential for future single chip packages has the wafer level approach: the package is completed directly on the wafer, then singulated by dicing for assembly in a flip chip fashion. The technological structure of this double-ball CSP is a pad redistributed die with a solder ball array a stress compensation layer (SCL) embedding the solder balls before a second set of solder balls is stencil printed or placed on top of the embedded balls. The reliability of the wafer-level CSP presented here was evaluated. The test chip was a 1 cm/spl times/1 cm square chip which was redistributed to an 14/spl times/14 ball array with a pitch of 0.5 mm. JEDEC level 3, 1000 cycles AATC (-55/spl deg/C/+125/spl deg/C) and 48 h autoclave on component level were passed. On board level 1000 hours humidify storage at 85/spl deg/C (85/85 test) was passed and only 20% of the WL-CSPs had opens after 1000 cycles -55/+125/spl deg/C.