Alternate solder bump technologies for flip chip applications

Flip chip on board technology using eutectic Sn-Pb solder bumps to reduce cost associated with cladded printed circuit board is becoming more common in the industry. However, the, low melting eutectic Sn-Pb bumps are subjected to issues such as solder extrusion during subsequent reflow processes and solder microstructure coarsening after extensive high temperature exposures such as the under-the-hood automotive environment. To address these issues, we have developed a stencil print solder bumping process that is applicable to various alternatives to eutectic Sn63Pb37 solder bump. The process has been demonstrated to solder alloys with melting range between 211/spl deg/C and 265/spl deg/C. Many alloys of such melting range have potential to meet temperature hierarchy requirement for flip chip BGA packages. Additionally, some high temperature solders contain no lead, which is good for environment and for reducing soft error rate of memory IC's. This paper summarized the alternate solder bump technology development, which uses the print solder bump process, the most flexible method to deposit the many bump metallurgies. Solder paste material down selection, process development, bump characterization, and flip chip interconnect reliability results for various alloy bumps are reported. Typical bump height uniformity is 135/spl plusmn/3.5 /spl mu/m, which is equivalent of 3% of bump height standard deviation. In many cases, bump composition is close to the theoretical eutectic composition of selected alloy systems. Preliminary reliability evaluation of direct chip attach packages having high m.p. bumps under-65/spl deg/C/+150/spl deg/C air-to-air temperature cycle test are reported.