Timing and control requirements for a 32-channel AMU-ADC ASIC for the PHENIX detector

A custom CMOS Application Specific Integrated Circuit (ASIC) has been developed consisting of an analog memory unit (AMU) and analog to digital converter (ADC), both of which have been designed for applications in the PHENIX experiment. This IC consists of 32 pipes of analog memory with 64 cells per pipe. Each pipe also has its own ADC channel. Timing and control signal requirements for optimum performance are discussed in this paper.