STG timing extensions and simulation

The Signal Transition Graph (STG) model-a specification form that is widely used for asynchronous circuits' behavior specification is extended to allow delay information specification. Timed STG models and their firing semantics are defined. Then the authors present an automatic technique for timed STG behavior specification in VHDL. The resulting VHDL specification may be used to simulate STG behavior with the specified delays. The requirements imposed on the STG to allow the joint environment-circuit behavior simulation are defined. Joint simulation of a circuit synthesized from STG with its environment is also presented.