An Asynchronous Dataflow Signal Processing Architecture to Minimize Energy per Op

Recent data shows that Dennard's law, which dictates the energy efficiency of digital transistors as their size shrinks, has failed in sub-100nm processes. New architectural paradigms need to be pursued to address the ever-increasing energy efficiency demands of commercial and military systems. This work presents a new dataflow architecture implemented with asynchronous circuits and laid out in a 45nm process. The work is derived from our previous work in developing a fully programmable architecture we call the Field Programmable Compute Array (FPCA), which was implemented using synchronous circuits. We present the results of our work to implement a FIR filter constructed using this paradigm. The asynchronous results are compared with a synchronous version of the same filter that was built using a standard-clocked digital-logic automated design flow. We simulated using an extracted layout and the results show significant improvement in cycle time, frequency and efficiency. The asynchronous pipeline has an overall efficiency improvement of 6.57 times that of the synchronous pipeline. We also show that in the asynchronous design we were able to scale the supply voltage from nominal down to 200mV, which results in even greater efficiency. This paper includes a discussion regarding the property of dataflow elasticity, which is needed for full programmability. Finally, we detail how to construct the circuits necessary to create this new type of pipeline.