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To handle complexity in large scale control problems, a popular approach is to impose hierarchical control structures. Hierarchical control can be interpreted as an attempt to handle complex problems by decomposing them into smaller subproblems and reassembling their solutions into a “functioning” hierarchical structure. It typically involves a number of control layers operating on different time scales that may be clock driven or event driven. Signals on different levels of the control hierarchy may be of different granularity representing phenomena like measurement aggregation when passing from lower to higher level control. Within a suitable formal framework guaranteeing certain consistency conditions, complexity reduction is achieved by interpreting specifications for lower control levels as abstractions of the plant under low level control. An essential task within a hierarchical control synthesis procedure is then to come up with a suitable choice of specifications for the individual control layers. Because of the dual role of these specifications, this typically involves a non-trivial trade-off. E.g., imposing a less strict specification for a control layer will facilitate the control synthesis task for this layer, but will make the control synthesis task for higher level control more difficult. In this paper, this trade-off is formally investigated for a specific scenario, where the top control layer is only responsible for the timing of certain discrete events, and where the abstraction it is based on can be represented by a timed event graph (TEG).