Latchup in CMOS technologies

It is shown how a conceptually simple definition of a pnpn structure's blocking state is also a precise statement of when latchup occurs, a statement that leads to a concise (there are no fitting parameters), experimentally verified equation for switching current. The operational pnpn configurations for various triggering modes are classified, and it is shown how they reduce to two simple analyzed cases. Latchup avoidance techniques are discussed from the perspective of the new latchup criterion.