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3D IC integration is nowadays considered as the most promising technology for extending the scaling concept of Moore's Law. By using TSVs (Thru Silicon Vias) it is possible to vertically stack IC devices and increase device functionalities without requiring transistors shrinkage and/or 2D sizes increase . 3D stacking is anyway a relative new technology and many issues and concerns are still to be resolved before moving to high volume manufacturing. This work describes the learning and the results achieved by manufacturing and stacking “ultra-thin” IC components with TSVs. We report on the main processes required for device manufacturing like backside RDL (Re-Distribution Layer) and μbumping; we also reports on the approaches used for 3D stacking and the effects observed by using NUF (No Flow Under Fill) and WAUF (Wafer Applied Underfill) . We finally present the results coming from wafers and 3D stacks characterization.