Design of low phase noise and fast locking PLL frequency synthesizer

Third-order charge-pump PLL frequency synthesizer is designed, considering phase noise and lock time. Using of bandwidth optimization, dead-zone eliminated, high-match charge pump, and low noise oscillator design methods to optimize system phase noise and also reduce lock time. Test shows that PLL frequency synthesizer output phase noise is −96.2dBc@1MHz, RMS jitter is 1.4ps, and lock time is about 2us.