Scaling CMOS Design Rules for HighTemperature Latchup Immunity

Existing and emerging needs in the automotive, aircraft, space, and well-logging industries call for operation of electronics at higher temperatures than the traditional 125°C. Temperature requirements for many of these applications, however, do not exceed 250°C. Extending the operation of low-cost junction-isolated CMOS to this temperature is feasible through straightforward changes in process technology, circuit styles, and layout design rules. The greatest challenge in using bulk CMOS at high temperature is latchup, which can be triggered by junction leakage. This article presents an empirical model for the holding voltage of CMOS latchup, which can be used to scale the design rules in a way that maintains latchup robustness at higher temperatures.