A PhaseLocked Loop with Digital Frequency Comparator for Timing Signal RecoveryThis work was supported by Telecomunicaes do Brasil S/A, under contract TELEBRS/UNICAMP 139/76.

A Phase-Locked - Loop with a Digital Frequency Comparator for clock extraction in a PCM regenerative repeater is presented. With such a Frequency and Phase-Locked - Loop (FPLL) it is possible to extract the timing signal in a PCM repeater without resort to stable and expensive Voltage Controlled Oscillators. In addition, a small noise bandwidth and a wide pull-in range can be easily obtained, thus improving performance and increasing reliability. Unlike previous solutions which use analog frequency comparators, here we present a completely digital frequency comparator which is simple to implement and which presents a wide margin against spurious outputs produced by input jitter.