A 30128 MHz Frequency Synthesizer Standard Cell

A frequency synthesizer standard cell, with an output frequency range of 30 - 128 MHz, has been implemented using a 1.0 µm (drawn), double level metal, double level poly, n-well CMOS process. The cell area is about 2100 mil². The synthesizer is implemented using a programmable, third order, charge-pump phase-locked loop with a sequential logic phase/frequency detector. An on-chip loop filter is used to eliminate any required off-chip components. A jitter standard deviation of 50 pS was measured at an output frequency of 100 MHz, using an external 10 MHz reference. The supply current required by the synthesizer cell alone was 9.0 mA, with a total current of 15.0 mA when the feedback, reference, and output counters are included.