A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors

A microprocessor clock generator based upon an analog phase-locked loop (PLL) is described for deskewing the internal logic control clock to an external system clock. This PLL is fully integrated onto a 1.2-million-transistor microprocessor in 0.8-µm CMOS technology without the need for external components. It operates with a lock range from 5 up to 110 MHz. The clock skew is less than 0.1 ns, with a peak-to-peak jitter of less than 0.3 ns for a 50-MHz system clock frequency.