A Monolithic 480 Mb/s Parallel AGC/Decision/ClockRecovery Circuit in 1.2m CMOS

A parallel architecture for high-data-rate AGC/decision/clock-recovery circuit, recovering digital NRZ data in optical-fiber receivers, is described. Improvement over traditional architecture in throughput is achieved through the use of parallel signal paths. An experimental prototype, fabricated in a 1.2-µm double-poly double-metal n-well CMOS process, achieves a maximum bit rate of 480 Mb/s. The chip contains variable gain amplifiers, clock recovery, and demultiplexing circuits. It yields a HER of 10^{- 11} with an 18 mV p-p differential input signal. The power consumption is 900 mW from a single 5 V supply.