A PLLBased 2.5Gb/s GaAs Clock and Data Regenerator IC

A GaAs IC that performs clock recovery and data retiming functions in 2.5-Gb/s fiber-optic communication systems is presented. Rather than using surface acoustic wave (SAW) filter technology, the IC employs a frequency- and pbase-lock loop (FPLL) to recover a stable clock from pseudorandom NRZ data. The IC is mounted on a 1-in X 1-in ceramic substrate along with a companion Si bipolar chip that contains a loop filter and acquisition circuitry. At the SONET OC-48 rate of 2.488 Gb/s, the circuit meets requirements for jitter tolerance, jitter transfer, and jitter generation. The data input ambiguity is 25 mV while the recovered clock bas less tban 2° rms edge jitter. The circuit functions up to 4 Gb/s with a 40-mV input ambiguity and 2° nos clock jitter. Total current consumption from a single 5.2-V supply is 250 mA.