Ground noise minimization in integrated circuit packages through pin assignment optimization

Due to suboptimal assignment of pins to grounds and signals, the ground noise problem in integrated circuit (ICs) packages either persists or compromises the design by forcing too many pins to be wasted carrying ground reference. This paper proposes a new CAD technique for optimizing pin assignment in IC packages to minimize ground noise using simulated annealing. Optimization techniques are used in which the objective function is the ground noise as determined by simulation of the IC package leadframe. However, modeling and simulation methods currently employed are prohibitively expensive in terms of CPU time. For this reason, two circuit models of the leadframe are developed and used concurrently: one to provide accuracy and the other to ensure fast execution. Using simulated annealing with a ground noise cost function has provided an observed 26-fold reduction in ground noise in a 208-pin IC quad flat pack (QFP) from a poor initial configuration. In addition, the same process was able to produce a 2.2-fold improvement when an intelligent initial pin assignment was used. Furthermore, these results came at a CPU cost of about 1200 s each on a SUN SPARC10 workstation.