A memory control chip for formatting data into blocks suitable for video coding applications

Most compression algorithms for motion television require large data storage, usually several television fields, and typically operate on blocks of data. A chip has been built to support both of these features. It generates, from a single clock source, all of the control and address signals required by standard off-the-shelf dynamic RAMs (DRAMs). This includes data packing and unpacking and automatic refresh when required. Counters are provided to address the data into and out of the memories of the form of blocks. The block sizes and field dimensions are programmable and are independent for both read and write operations. Thus, one set of counters can be programmed for sequentially scanned data coming from a camera or going to a television monitor, and other set of counters can be programmed for the block size employed in the compression hardware. Blocks of data can be accessed either continuously or one at a time. When data are read from the memories, a single pel-width pulse marks the start of valid data. Signals marking both end of the block and end of field have also been provided to ease system interfacing.<
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