Low-complexity distributed parallel processor for 2D IIR broadband beam plane-wave filters

Real-time systolic-array-based implementations of VLSI two-dimensional (2D) infinite-impulse-response (IIR) frequency-planar beam plane-wave filters have potentially wide applications in the filtering of spatio-temporal RF broadband plane waves based on their directions of arrival (DOAs). Distributed-parallel-processor (DPP) implementations of the systolic arrays allow synchronous sampling of the 2D input signal array, but because of the direct-form structure they have high circuit complexity. To address the high-complexity problem, the differential-form 2D z-domain transfer function is employed here to obtain a novel DPP systolic-array-based filter architecture. Differential operators are obtained by applying elemental predistortion to the passive LR prototype filter network using series-connected negative-resistance elements. The proposed systolic 2D IIR architecture is implemented on a single Xilinx Virtex-4 Xc4v Sx35-10ff668 FPGA chip. Two examples of broadband plane-wave filtering supporting N = 32 and N = 64 sensors are reported. On-chip test results are achieved using stable real-time tests at frame sample frequencies of up to 90MHz as well as stepped hardware cosimulation in conjunction with a parallel-operating MATLAB/Simulink simulation.