A 6-10 bits Reconfigurable 20MS/s Digitally Enhanced Pipelined ADC for Multi-Standard Wireless Terminals

A 20MS/s pipelined ADC architecture can be reconfigured in 10 clock cycles to resolve 6, 8, 9 or 10 bits at maximum resolution. A 9.1bit ENOB and 74dB SFDR with a power consumption of only 8mW was achieved by using background digital calibration and op-amp sharing techniques. The test chip, containing two ADC for I and Q processing within a wireless receiver, has been realized in a 0.13mum pure CMOS technology and uses 3.2mm
²
silicon area