Highly parallel VLSI architectures for the 2-D DCT and IDCT computations

A new systolic array without matrix transposition hardware is proposed to compute the two-dimensional discrete cosine transform (2-D DCT) based on the row-column decomposition. This architecture uses N/sup 2/ multipliers to evaluate N/spl times/N-point DCT's at a rate of one complete transform per N clock cycles, where N is even. It possesses the features of regularity and modularity, and is thus well suited to VLSI implementation. As compared to existing pipelined regular architectures for the 2-D DCT, the proposed one has better throughput performance, smaller area-time complexity, and lower communication complexity. The new idea for the 2-D DCT is also extended to derive a similar systolic array for the 2-D inverse discrete cosine transform (IDCT). Simulation results demonstrate that the proposed 2-D DCT and IDCT architectures have good fixed-point error performance for both real image and random data. As a consequence, they are useful for applications where very high throughput rates are required.<
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