Numerical Comparison of Packaging Technologies for Power Electronics Modules

In this paper we present a comparison of the parasitics induced by the packaging structures in power electronic modules by means of numerical methods. The goals were to identify the critical substrate layouts and packaging components and to understand the mechanisms that affect the module's switching performance. The presented investigations compare the classical and widely used wire bonding technology with new area bonding techniques such as dimple array, metal post, and power overlay. Numerical analysis was done with a dedicated simulation platform based on a PEEC method solver and SPICE circuit simulations. A 1200 V/300 A IGBT module was used as a case study to illustrate the investigation results