A low-power system-on-chip for the documentation of road accidents

In this letter, the implementation of a system-on-chip for the documentation of road accidents is presented. Key features of the system are the implementation on a programmable architecture of a compression algorithm capable of encoding up to 20 black and white QCIF frames/s, and the computation of a digital signature performed every frame which is applied to the encoded bitstream certifying the source of the video sequence. The acquired images are then stored on a battery of on-chip flash memories that can be used to retrieve accident information to be used in legal confrontations. Having to perform in critical energy conditions (e.g., continued image acquisition for up to 10-20 s after an accident has occurred), the system was designed to minimize energy consumption at all levels. The system-on-chip has been implemented in 6/spl times/6 mm/sup 2/ on a 0.25-/spl mu/m 6-metal standard-cell CMOS technology and works at 40 MHz with a 2.5-V power supply. Performance can be decreased to 12 QCIF frames/s, 24 MHz, and 1.3-V power supply in order to achieve 30-mW power consumption.