MOS Compatibility of high-conductivity TaSi2/n+poly-Si gates

The MOS-VLSI parameters and process compatibility of a high-conductivity refractory silicide gate with a sheet resistance of ∼ 2 Ω/□ have been evaluated. The gate metallization typically consisted of 2.5 kÅ TaSi
2
/2.5 kÅ poly-Si, which was sintered prior to patterning with a CF
4
/O
2
plasma etch. Measurements were made to determine the metal work function, oxide fixed charge, surface-states density, dielectric strength, oxide defect density, lifetime, current leakage, and the flat-band voltage stability with respect to mobile charge contamination, slow trapping, and hot-electron trapping. On IGFET's (500-Å SiO
2
, As-implanted source/ drain), V
T
and β measurements were made as a function of the back-gate bias and the channel length as small as 2 µm. The MOS and IGFET parameters are nearly ideal and correspond to those expected of n
⁺
poly-Si gates. Static and dynamic bias-temperature aging stability of the V
FB
is excellent. These characteristics are preserved through subsequent standard VLSI process steps. However, certain process and structure limitations do exist and these have been defined.