Cost-size optima of monolithic integrated circuits

A generalized cost-size relationship is derived for a monolithic circuit consisting of N identical components, taking into account variations in component density, yield, and assembly costs with N. It is intended to reveal cost trends rather than give accurate results for specific cases and deals only with fabrication costs. A yield-area relationship is used which takes into account chip-to-chip variations in defect density. It is found that the ratio (circuit cost per component/cost of discrete transistor) is a minimum at a chip size which is determined primarily by the spot defect density on the device. This optimum chip size lies between approximately 20 and approximately 60 mils square for a wide range of parameter values. State-of-the-art parameter values indicate a potential order of magnitude cost saving in integrated circuits compared with discrete transistors. The minimum value for the cost ratio is in general inversely proportional to the maximum packing density of components on a semiconductor slice and has a limiting value approximately 1/8N, N
0
being the number of components which can be packed on the chip size normally used for transistors. Arrays of identical logic gates fit the circuit model used quite closely, and the curves indicate that the cost per gate in reasonably densely packed arrays can be less than the cost of a discrete transistor. The results also indicate that when systems requirements make it desirable to include larger numbers of components in one package than the optimum for one monolith, wired-chip schemes are preferable to single monoliths, the optimum chip size being smaller than that for a simple monolith.