The power of functional scaling: beyond the power consumption challenge and the scaling roadmap

The relentless progress of silicon technology in the last few decades has been astounding, owing to device scaling. The characteristic lengths associated with successive generations of the technology have decreased, producing higher performance devices and circuits. At various times, people have predicted the end of scaling because of apparent barriers, but these barriers have fallen thanks to the ingenuity of the scientists and engineers involved in the technology. This has occurred through developments and changes in device design, the introduction of new materials, improved processing technologies and tools - both engineering and simulation - and other innovative approaches. The resulting increases in the densities of devices and their functionality in circuits now make the issue of power dissipation, both static and dynamic, a serious constraint to future scaling advances. In this article, a new very large scale integration (VLSI) structure is proposed and demonstrated to address these issues, using the 3D integration of high performance Ge-on-insulator (GOI) field effect transistors above conventional interconnects and Si devices.