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A wideband phase-locked-loop (PLL) modulator for wireless applications is reported. This modulator is based on PLL fractional-N frequency synthesis techniques along with sigma-delta modulation to randomize fractional-N spurs. A modified sigma-delta function allows for suppression of sigma-delta noise at lower frequencies, and hence allows for wider loop bandwidth. Also, sigma-delta quantization noise is reduced by using fractional division ratios. Low-power and low-area algorithmic techniques are used in the modified sigma-delta modulator in order to make it a feasible option. It is shown that the resulting modulator meets the GSM specifications and has a total power consumption of 2 mW at 1-GHz operation.