Some Simulation Results for the Time to Indicate Phase Lock

A digital simulation of a second-order phase-lock loop (PLL) acquiring lock in the presence of noise is reported. Since the system simulated includes lock-indicating circuitry, a distinction is made between the time to phase lock and the time to indicate lock. The parameter of interest is the time to indicate lock. The major results of the simulation are estimates of 1) the mean time to indicate lock, and 2) the probability distribution function for the mean time to indicate lock. Results are presented for a wide range of signal-to-noise ratios and for input frequency offsets ranging from one-half to three times the phase-lock loop noise bandwidth. In each case 100 independent trials of the simulation were conducted to obtain the estimate. It is found that the mean time to indicate lock is relatively independent of signal-to-noise ratio (
S/N
) down to about
S/N = 10
dB. For greater values of
S/N
the mean time to indicate lock may be closely approximated by the time to indicate lock in the absence of noise. The results are compared with Viterbi's time to frequency lock and found in good agreement for the high
S/N
cases. Most of the difference is attributed to the time constant of the lock indicating circuitry. The system simulated is considered representative of many practical phase-lock receiving systems where there is a requirement for indicating acquisition of lock. Hence, the data presented in this paper can be used to good advantage for estimating the probability of acquiring and indicating lock in a specified time.