Maximally-Flat Time Delay Ladders

The driving-point impedance for a maximally-flat time delay response is derived. The impedance is synthesized as an infinite low-pass LC ladder that starts with an
\epsilon G/\omega_0
-farad shunt capacitor The ladder elements rapidly taper toward a capacitance of
2G/\omega_0
farads and an inductance of
2R/\omega_0
henries. The impulse and step responses of the impedance are derived as a series of Bessel functions. A three-terminal maximally-flat time delay transfer impedance is also considered. The conditions for a smoothly-tapering ladder structure are given. The transfer impedance is synthesized as an infinite low-pass LC ladder whose first two shunt capacitors are
32G/(9\omega_0)
and
\epsilon^{3}G/(9\omega_0)
farads, respectively. The impulse and step responses of the transfer impedance are also derived.