CMOS Latch-up Improvement: Embedded Active Collector in FinFET Technology

An embedded active collector is proposed for CMOS latch-up improvement. The implemented structures in FinFET technology are investigated through derived analytical model, TCAD simulation, and experiments. Active collector design shows a significant latch-up improvement by enhanced holding voltage and suppressed SCR turn-on. The high holding voltage sensitivity on anode-cathode spacing and active collector area offers excellent design capability for latch-up free CMOS.