A 0.3V-VIN, 0.015ps-FoM Fully Integrated Analog-Assisted Digital LDO With Dual-Negative Gate Control and Adaptive Transient Recovery Path

This letter presents a fully integrated analog-assisted (AA) digital low-dropout regulator (DLDO) to operate at low input voltage (
V
_IN
) with fast transient response. A negative voltage gate driver (NVGD) enables low-
V
_DS
triode operation and large current capacity of pass transistors even at low
V
_IN
of 0.3 V by utilizing a negative voltage. A dual negative voltage tank (DNVT) compensates for leakage in NVGD for reliable output regulation. An adaptive transient recovery path (ATRP) in AA loops expedites output voltage (
V
_OUT
) regulation against a large load current (
I
_LOAD
) step. The negative supply from DNVT also enhances inverter-based comparators in ATRP at low
V
_IN
. The proposed DLDO fabricated in a 28 nm complementary metal-oxide-semiconductor (CMOS) process operates at lowest
V
_IN
of 0.3—1 V with 50 mV dropout among state-of-the-art DLDOs. The DLDO consumes quiescent current of 23
μ
A, while providing large
I
_LOAD
up to 800 mA. The ATRP ensures small
V
_OUT
droop of 97 mV against
ΔI
_LOAD
of 380 mA, achieving a low figure-of-merit (FoM) of 0.015 ps.