A 0.1–3.5-GHz Inductorless Noise-Canceling CMOS LNA With IIP3 Optimization Technique

A new linearity optimization (LO) technique is proposed to improve the input third-order intercept point (IIP3) of the wideband noise-canceling (NC) low-noise amplifiers (LNAs) without any influence on input impedance matching. Furthermore, this technique can be combined with the
${gm}$
-boost technique and achieve LO with low power consumption. Fabricated in the 65-nm CMOS technology, the proposed wideband LNA occupies a small chip area of 0.0062 mm
²
. This LNA achieves 4–9.4-dBm IIP3, 17-dB voltage gain, and 2.09–3.2-dB noise figure (NF) over the entire frequency range from 100 MHz to 3.5 GHz. Furthermore, the core circuit draws only 6.6 mA from a single 1-V power supply.