25-GHz-band High Efficiency Stacked-FET Power Amplifier IC with Adaptively Controlled Gate Capacitor in 45-nm SOI CMOS

This paper presents a 2S-GHz-band high-efficiency power amplifier (P A) with a novel adaptively controlled gate capacitor circuit for 5th generation (5G) mobile terminal application in the 45-nm silicon on insulator (SOI) CMOS process. This novel gate capacitor circuit effectively controls the RF swing of each stacked FET to achieve high efficiency in the several-dB back-off region. The PA adopts a 4 stacked FET structure to increase the output power because of the low breakdown voltage issue of scaled MOS FETs. An adaptive bias circuit is employed for high linearity and high back-off efficiency. At a supply voltage of 4 V, the fabricated P A exhibited a saturated output power of 21.5 dBm, a peak power added efficiency (P AE) of 40.9%, a gain of 17.6 dB, and an ITRS FoM of 83.2 dB. The effective P A area was 0.55 mm by 0.4 mm.