InFO_oS (Integrated Fan-Out on Substrate) Technology for Advanced Chiplet Integration

The continuous pursuit of higher compute power with insatiable data bandwidth to meet relentless AI system demands from cloud computing, data centers, enterprise servers, supercomputers, network system and edge computing, has urged new system integration solutions with larger footprint, denser 3D interconnect, close proximity 3D inter-chip integration and new memory system. Recent years, chiplets integration has prevailed in high performance computing (HPC) for cost and performance consideration. For HPC networking applications, the network switch capacity has increased from 6.4 Tb/sec to 25.6 Tb/sec to meet ever-increasing big data growth in cloud and data center for AI training, deep learning, and inferencing. Single advanced node SoC switch chip solution no longer meets the switch capacity growing demand due to cost and performance consideration. To resolve this issue, we have developed InFO_oS (InFO on Substrate) technology featuring multiple tiers of high density
$2/2\mu\mathrm{m}$
RDL line width/space to integrate multiple advanced node switch chiplets for cost and performance. In this paper, we present the industry's first 2.5x reticle size of fan-out (2100 mm
²
) with
$110 \times 110\ \text{mm}^{2}$
substrate integration. The 2.5x test vehicle integrates 10 chiplets, 2 logic and 8 IO dies, through 5 layers of RDLs interconnection. Various stacking-via has been evaluated to provide more design flexibility and area miniaturization. InFO_oS is integrated on a wafer base, so it can fully leverage the tools, materials, process know-how, and manufacturing capacity of InFO technology platform for design flexibility, yield and fast time to market. Through process optimization, a promising high electrical yield has been achieved with D2D connection >95%. Process challenges and the results of component-level reliability (uHAST/TC/HTS) will be also addressed.